Parent Page: Digital Logic Design - Lab Tutorials

01 - Objective

In this tutorial, we discuss building a 4-bit counter.

02 - Logic Gates Implementation

The following code defines a 4-bit counter entity, which takes in a clock signal, a clear signal, and count signal. It outputs 4-bit value of the current count.

library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------------------------
entity counter is

generic(n: natural :=4);
port(
	clock:	in  std_logic;
	clear:	in  std_logic;
	count:	in  std_logic;
	Q:		out std_logic_vector(n-1 downto 0)
);
end counter;
----------------------------------------------------
architecture behv of counter is		 	  
    signal Pre_Q: std_logic_vector(n-1 downto 0):="0000";
begin
    -- behavior describe the counter
    process(clock, count, clear)
    begin
	if clear = '1' then
 	    Pre_Q <= std_logic_vector(unsigned(Pre_Q) - unsigned(Pre_Q));
	elsif (clock='1' and clock'event) then
	    if count = '1' then
		Pre_Q <= std_logic_vector(unsigned(Pre_Q) + 1);
	    end if;
	end if;
    end process;	
	
    -- concurrent assignment statement
    Q <= Pre_Q;
end behv;
-----------------------------------------------------

The testbench includes a clock process that generates a clock signal with a period of 10 ns. It also includes a stimulus process that provides input signals to the counter entity. Initially, the clear signal is high. After 20 ns, the clear signal is set low, and the count signal is set to high, in order to start counting.

library ieee;
use ieee.std_logic_1164.all;			 
use ieee.numeric_std.all;

entity counter_TB is			-- entity declaration
generic(n: natural :=4);
end counter_TB;
-----------------------------------------------------------------------
architecture TB of counter_TB is

  component counter
  port(   clock:	in std_logic;
    clear:	in std_logic;
    count:	in std_logic;
    Q:		out std_logic_vector(n-1 downto 0)
  );
  end component;

  signal T_clock:     std_logic;
  signal T_clear:     std_logic;
  signal T_count:     std_logic;
  signal T_Q:         std_logic_vector(n-1 downto 0);
begin
  U_counter: counter port map (T_clock, T_clear, T_count, T_Q);

  process				 
  begin
		T_clock <= '0';			-- clock cycle is 10 ns
		wait for 5 ns;
		T_clock <= '1';
		wait for 5 ns;
  end process;

  process
		variable err_cnt: integer :=0;
  begin											
		T_clear <= '1';			-- Clear output
		T_count <= '1';
		wait for 20 ns;	
	
		T_clear <= '0';			-- Release the clear - Start counting
	
		-- test case 1
		wait for 10 ns;
		assert (unsigned(T_Q)=1) report "Failed case 1" severity error;
		if (unsigned(T_Q)/=1) then
		    err_cnt := err_cnt+1;
		end if;
	
		-- test case 2
		wait for 10 ns;
		assert (unsigned(T_Q)=2) report "Failed case 2" severity error;	
		if (unsigned(T_Q)/=2) then
		    err_cnt := err_cnt+1;
		end if;
				
		-- test case 3
		wait for 10 ns;
		assert (unsigned(T_Q)=3) report "Failed case 3" severity error;
		if (unsigned(T_Q)/=3) then
		    err_cnt := err_cnt+1;
		end if;
				
		-- test case 4
		wait for 10 ns;
		-- test case 5
		wait for 10 ns;
		-- test case 6
		wait for 10 ns;
		-- test case 7
		wait for 10 ns;
		-- test case 8
		wait for 10 ns;
		-- test case 9
		wait for 10 ns;
		-- test case 10
		wait for 10 ns;
		-- test case 11
		wait for 10 ns;
		-- test case 12
		wait for 10 ns;
		-- test case 13
		wait for 10 ns;
		-- test case 14
		wait for 10 ns;
		-- test case 15
		wait for 10 ns;
		-- test case 16
		wait for 10 ns;
		assert (unsigned(T_Q)=0) report "Failed case 16" severity error;
		if (unsigned(T_Q)/=0) then
		    err_cnt := err_cnt+1;
		end if;
		-- test case 17
		wait for 10 ns;
		-- test case 18
		wait for 10 ns;
		-- test case 19
		wait for 10 ns;
		-- test case 20
		wait for 20 ns;	
		T_clear <= '1';
		wait for 40 ns;	
		T_clear <= '0';			-- resume counting
		wait;
  end process;
end TB;

03 - Simulation Process

04 - Flashing Process

Please follow the same steps found in lab-03 in order to synthesize and flash the FPGA.

05 - Task

Design and build using VHDL a 4-bit counter that counts from 0 to 10 only; such that when counter value reaches 10, counter resets to 0.