Steps to simulate the design are given below:

1. Analysis of design and test bench files:

Commands given below are used to analyze the design files present in directory LIB1/, RTL/ and TB/. VHDL files present in LIB1/ are compiled in library ‘lib1’, while VHDL files present in directories RTL/ and TB/ are compiled into library ‘work’.

ghdl -a *.vhd --ieee=synopsys

2. Elaboration of design and test bench

ghdl -e file_tb --ieee=synopsys

3. Running simulation:

command given below is used to run executable for 1 ms and dump simulation results into file output.vcd.

ghdl -r file_tb --stop-time=1ms --vcd=file.vcd

3. To observe waveform use following command.

gtkwave file.vcd

Result

Resource:

http://www.cdeep.iitb.ac.in/slides/A09/EE705/EE705-L22.pdf