[Dataflow, Behavioral, Structural]

1. Dataflow Architecture

• Uses only concurrent signals assignment statements.

• Describes a system in terms of how data flows through the system.

• Data dependencies match those in a hardware implementation.

• Directly implies a corresponding gate-level implementation.

Example:

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
	port (
		a, b: in std_logic;
		sum, carry_out: out std_logic
	);
end half_adder;

architecture dataflow of half_adder is
begin
	sum <= a xor b;
	carry_out <= a and b;
end dataflow;

2. Behavioral Architecture

• Uses only process statements.

• Describes a system’s behavior or function in an algorithmic fashion.

• The most abstract style.

• It doesn’t directly imply a particular gate-level implementation.

• Consists of one or more process statements.

• Each process statement is a single concurrent statement that itself contains one or more sequential statements.

Example:

library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
	port (
		a, b: in std_logic;
		sum, carry_out: out std_logic
	);
end half_adder;

architecture behavior of half_adder is
begin
	ha: process (a, b)
	begin
		if a = ‘1’ then
			sum <= not b;
			carry_out <= b;
		else
			sum <= b;
			carry_out <= ‘0’;
		end if;
	end process ha;
end behavior;

3. Structural Architecture

• Uses only component instantiation statements.

• Entity is described as a set of interconnected components.

• The Top-Level design entity’s architecture describes the interconnection of lower-level design entities.

• Each lower-level design entity can, in turn, be described as an interconnection of design entities.

• Most useful and efficient when a complex system is described as an interconnection of moderately complex design entities.

• This approach allows each design entity to be independently designed and verified before being used in the higher-level description.

Example:

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is                     -- Entity declaration for half adder
	port (
		a, b: in std_logic;
		sum, carry_out: out std_logic
	);
end half_adder;

architecture structure of half_adder is     -- Architecture body for half adder
	component xor_gate                    -- xor component declaration
		port (
			i1, i2: in std_logic;
			o1: out std_logic
		);
	end component;
	component and_gate                    -- and component declaration
		port (
			i1, i2: in std_logic;
			o1: out std_logic
		);
	end component;
begin
	u1: xor_gate port map (i1 => a, i2 => b, o1 => sum);
	u2: and_gate port map (i1 => a, i2 => b, o1 => carry_out);
	-- We can also use Positional Association
	-- => u1: xor_gate port map (a, b, sum);
	-- => u2: and_gate port map (a, b, carry_out);
end structure;

Resources

• [https://buzztech.in/vhdl-modelling-styles-behavioral-dataflow-structural/#:~:text=The difference between these styles,uses only component instantiation statements](https://buzztech.in/vhdl-modelling-styles-behavioral-dataflow-structural/#:~:text=The%20difference%20between%20these%20styles,uses%20only%20component%20instantiation%20statements)